Journal of Circuits, Systems and Computers

Artificial Intelligence (AI) is rapidly transforming the healthcare, finance and transportation industries. This paper presents a field-programmable gate array (FPGA)-based neural network accelerator (NNA) design for power allocation in downlink nonorthogonal multiple access (NOMA) networks. The proposed hardware accelerator effectively cuts computational costs while delivering performance on par with the highest sum capacity. Numerical results show that this NNA offers a remarkable computational speed increase of up to 99% compared to the conventional exhaustive search method. Furthermore, the deep learning (DL) model achieved high accuracy (0.92 training, 0.93 testing), and the hardware accelerator design for this DL inference model was implemented on the PYNQ-Z2 board-constrained edge device to predict power allocation coefficients in NOMA systems.

This paper presents a complementary split-ring resonator (CSRR) loaded coplanar waveguide (CPW) fed with a circular shape, miniaturized diamond slot planar monopole antenna. The proposed antenna for healthcare monitoring biomedical applications uses the industrial medical and scientific band. The antenna design and development to implant the human phantom are proposed. The primary goal of this work is to continuously monitor the patient’s ability to detect abnormal conditions as soon as possible as a result of improvements in quality of life. In this case, an antenna design methodology must prioritize features such as miniaturization, increased gain and bandwidth, and biocompatibility. Simulated and measured antenna characteristics for biomedical applications are performed at ISM Band frequency.

This paper introduces a low-power fully differential fixed window level-crossing analog-to-digital converter (LC-ADC) for wireless medical implantable devices. The LC-ADC could be an excellent candidate for low-power systems due to the reduction of sampling points for bio-potential signals. Different from existing fixed window LC-ADCs, which use a 1-bit DAC or scaler and two reference levels to move the input signal to the comparison window, a simplified scheme is proposed in which the DAC or scaler is removed and a single-reference level is used to create the comparison window. The proposed LC-ADC utilizes a single-reference comparator, which leads to a simplified implementation and significant reduction in power consumption and circuit area. In addition, using a single reference level and removing DAC, leads to a decrease in the complexity of the controlling logic. The proposed LC-ADC is simulated in 0.18 $\mu$m CMOS technology. The simulation results achieve an effective number of bits (ENOB) of up to 6.5 bits with about 59–141 nW power consumption under 0.8 V supply and input signal bandwidth from 5 Hz to 4 kHz.

The electronically tunable differentiator using a voltage difference transconductance amplifier (VDTA) is proposed, designed, and analyzed. The simulation was done using the Cadence Virtuoso tool of 45 nm CMOS technology with a supply voltage of ±0.9 V. The maximum power consumption of the proposed circuit is 246 $\mu$W with a total harmonic distortion of 5.4%. The output can be tuned using four parameters: $g_{m1}$, $g_{m2}$, $R_1$, and $R_2$. The transconductance can be varied using bias current and aspect ratio of CMOS transistors. The utilized area of VDTA layout is 1075.81 $\mu$m². The parasitic impedance affects the output of post-layout simulation and causes little delay compared to schematic. The design has been experimentally verified using LM13700 integrated circuit. The results of the proposed circuit show good agreement with the experimental results and mathematical expressions. The proposed circuit can be used as a tunable PD controller, in which the voltage gain of the proposed circuit is $G_{\mathrm{\text{PD}}}=K_p+S{K}_d$. The design is versatile and can be used in different applications such as temperature control systems, photo voltaic cells, waveform generators, microwave communications systems, and instrumentation systems.

The phase and gain imbalance of a balun output can be adjusted by a differential current balancer (DCB) circuit. The performance of DCB circuit, for correcting the phase (gain) imbalance, is analyzed for a wide range of input signal level, and the accuracy is verified with circuit simulation. To illustrate the phase-error/gain-error (PE/GE) correction, a 30–40 GHz DCB circuit is designed and simulated in a 180-nm CMOS process. The DCB is examined for input PE, $\mathrm{\Delta }{𝜃}_A$, of $-20^{\circ }\le \mathrm{\Delta }{𝜃}_A\le +20^{\circ }$ and input GE, G_A, of $-2$dB$\le 20^{\ast }$ log $(1+G_A)\le +2$ dB. Analysis and simulation illustrate an output phase error (OPE_DCB) of $-10^{\circ }\le {\mathrm{\text{OPE}}}_{\mathrm{\text{DCB}}}\le +2^{\circ }$ and output gain error (OGE_DCB) of $-1$ dB $\le {\mathrm{\text{OGE}}}_{\mathrm{\text{DCB}}}\le +1.5$ dB, over frequency range of 20–50$$GHz. The results of DCB circuit for PE (GE) compensation are compared to that of phase-correction technique (PCT) circuit, illustrating the superior phase (gain) imbalance correction of the DCB circuit with lower NF and DC power consumption.

Artificial Intelligence (AI) schemes eliminate the need for intellectual human knowledge of crypto algorithms to facilitate side-channel attacks on security implementations. Side channel attack analysis for circuit-level hardware (VLSI) implementations of symmetric-key block ciphers through artificial machine models are yet to be addressed. The proposed design of block cipher architecture, which is the implementation under attack features, secure adiabatic logic style the Charge Balancing Symmetric Pre-resolve Adiabatic Logic (CBSPAL). This style exhibits uniform power consumption through its inherent circuit arrangement, which makes it robust toward side-channel power attacks. This paper considers several Multilayer Perceptron (MLP) architectures to mount non-profiled side-channel attacks on round 1- PRESENT circuit-level implementation. Supervised learning of the MLP models through training with power waveforms employs binary LSB labeling. An attack on the custom dataset with 50,000 supply power traces collected from the CBSPAL implementation fails to retrieve secret information in any of the 8 bytes. The traditional Correlation Power Attack (CPA) was also not thriving with the proposed implementation. Comparison is made through a similar attack approach on benchmark AES (ASCAD dataset), which distinguishes the secret information throughout all the parameters of interest: normalized accuracy, normalized NMM accuracy and rank plots on byte 3.

Aiming at the noise that may exist in the data collection and transmission of power system synchronous phasor measurement unit (PMU), as well as the imbalance between stable and unstable samples, making the model likely to tilt to most kinds of samples, thus affecting the evaluation results of power system transient stability model, a transient stability assessment method integrating Convolutional Block Attention Module (CBAM) and deep residual shrinkage network is proposed. First, the mapping relationship between the input values and the labels of the stability results is established, and the electrical quantities are transformed into the form of convolutional feature maps to be input into the model. Second, channel attention module and spatial attention module are introduced, and soft threshold function is used to automatically learn the noise threshold and reduce the interference of the noise. As the model tends to favor the majority of the samples during training, gradient harmonized mechanism (GHM) loss function is introduced to improve the attention of the minority of samples as well as the training effect and evaluation performance of the model. Finally, the model is tested by simulation on the IEEE39 node system.

In video action recognition, effective spatiotemporal modeling is crucial. However, traditional two-stream methods face challenges in integrating spatial information from RGB images and temporary information from optical flow without long-range temporal modelling. To address these limitations, we propose the Deep Fusion Module (DFM), which focuses on the deep fusion of spatial and temporal information and consists of two components. First, we propose an Attention Fusion Module (AFM) to effectively fuse the shallow features obtained from a two-stream network, thereby facilitating the integration of spatial and temporal information. Next, we incorporate a SpatioTemporal Module (STM), comprising a ConvGRU and a 1×1 convolution, to model long-range temporal dependency and fuse spatial-temporal features. Experiments on the UCF101 dataset show that our method achieves 96.5% accuracy, outperforming baseline two-stream models by 0.3%.

In this research, we present a 16-bit multi-mode digital-to-analog converter (DAC) with a time-interleaved (TI) structure operating at a frequency of 4 GHz over a bandwidth (BW) of 20 MHz, which is in compliance with the fifth generation (5G) wireless communications. The proposed architecture uses only one clock frequency to generate radio frequency (RF) signals and includes a second-order (2nd-order) delta-sigma modulator (DSM) with a reconfigurable low-pass (LP) mode, band-pass (BP) mode at Fs/4, and high-pass (HP) mode for signal synthesis. To increase the sampling frequency (Fs) of the TI structure, four channels are proposed, each working at a frequency of Fs/4. Since there are simple coefficients for all modes, the multiplication operation can be performed using a shifter block. This leads to design simplification, lower power consumption, smaller occupied area, and higher speed. A major challenge in designing this type of structure is the duty-cycle-error (DCE), especially in interleaved mode. In this research, we propose a new solution that solves DCE-related problems without adding digital circuits to the output of the DSM, by adjusting the analog filter circuit. Simulation results in MATLAB show that the value of signal-to-noise and distortion ratio (SNDR) in LP is equal to 106.14 dB, in BP is equal to 107.84 dB, and in HP is equal to 105.34 dB. Compensating for filters increases the spurious-free dynamic range (SFDR) to more than 118 dB.

This paper presents an innovative general structure for a single-loop Sigma-Delta ($\mathrm{\Sigma }\mathrm{\Delta }$) modulator that combines low-distortion and noise-coupled techniques to achieve high-resolution for low-power applications. The low-distortion technique adjusts the signal transfer function of the proposed structure to unity, while the noise-coupled technique enhances the order of quantization noise-shaping at the modulator output. These techniques were incorporated into the design to increase the modulator order without requiring additional operational amplifiers during its circuit implementation, resulting in a low-power modulator compared to similar structures. To reduce the number of required amplifiers, a second-order infinite impulse response (IIR) filter was used in the modulator loop filter, in place of two integrators. To assess the proposed structure’s performance, a third-order modulator sample was implemented and simulated for speech recognition applications, specifically, digital hearing aids, using 180 nm complementary metal oxide semiconductor (CMOS) technology. The results indicate that for a third structure with a sampling rate of 64, an input sine signal of −6 dBFS and a sampling frequency of 2.56 MHz, the signal to noise plus distortion (SNDR) was 81.9 dB, and the dynamic range (DR) was 88 dB for a 20 KHz bandwidth. The modulator’s power consumption was 126.9 $\mu$W. Circuit and system-level simulations demonstrate the effectiveness of the proposed method.

Designing high-speed and energy-efficient blocks for image and digital signal processing (DSP) architecture is an evolving research field. This work designs a high-speed and energy-efficient multiply-accumulate (MAC) unit to augment the performance of field-programmable gate array (FPGA)-based accelerators and softcore processors. In this work, three discrete 32-bit fixed-point signed MAC architectures were designed in Verilog and synthesized for the Zynq 7000 ZedBoard to obtain efficient MAC architecture. The ultimate goal of this work is to design a fast and energy-efficient MAC unit that can achieve speed up to the DSP48 block to reduce the latency of IoT edge computing. Energy efficiency was achieved in PPG and partial product addition (PPA) for the proposed Booth radix-4 Dadda (BR4D)-based MAC. At PPG, the width of the partial product (PP) terms was optimized with Bewick’s signed extension to reduce the power consumption. At PPA, the number of PP rows reduces the critical path delay (CPD) with Dadda-based PPA. The proposed BR4D MAC unit offers a reduction in dynamic power, CPD, power-delay product (PDP) and energy-delay product (EDP) by 22%, 9%, 29% and 36%, respectively, compared to standard Booth radix-4 Wallace tree (BR4WT) based MAC. Furthermore, hybrid MACs (BR4WT and BR4D) were compared with the current state-of-the-art (SoA) designs, and it was found that the proposed BR4D MAC is 47% faster compared to the same design in SoA. The proposed BR4D was tested for frequency scaling technique by reducing the frequency in steps of 10 MHz from a maximum usable frequency (MUF) of 64 MHz to 10 MHz to evaluate the performance for low-power applications. Reducing clock frequency by 84% will reduce the power consumption at the same proportion and speed by 38%. Additionally, the proposed design helps to improve the battery life of IoT end nodes with a reduction in energy consumption and EDP by 76% and 61%, respectively.

The fast warning for financial risk of enterprises has always been a realistic demand for their managers. Currently, this mainly relies on expert experience to make comprehensive analysis from massive business data. Benefitting from the strong computational performance of deep learning, this paper proposes a fuzzy neural network (FNN)-based intelligent warning method for financial risk of enterprises. An improved FNN structure with time-varying coefficients and time-varying time lags is established to extract features of enterprises from complex financial context. The algorithm of fuzzy C-means and fuzzy clustering based on sample data are studied. In this paper, the fuzzy C-means algorithm is used to cluster the samples, the input sample set is preprocessed, a new set of learning samples is formed, and then the neural network is trained. The enterprise financial risk sample and its modular FNN model are established, and the evaluation of the enterprise financial risk sample is simulated. Then, a decision part is added following the FNN part to output the warning results. After that, we have also conducted a case study as simulation experiments to evaluate the proposed technical framework. The obtained results show that it can perform well in the fast warning of financial risk for enterprises.

This paper presents the structure and operational principles of high-frequency electronically controllable sinusoidal oscillators employing current-feedback operational amplifiers (CFOAs) with externally accessible compensation node $z$ as active components. The resonant circuits in the oscillators are connected to the terminal $z$, and for them in the selective network varactor diodes or varicaps as the variable capacitances are utilized, which are controlled by external DC voltage. Based on an analysis of the proposed circuit configurations, analytical expressions for the characteristic equation in a steady-state mode of operation and formulas for the basic electrical parameters have been obtained. In order to verify the functionality of the proposed electronic circuits and the effectiveness of the derived analytical expressions, an experimental and simulation study of sample electronic circuits with commercially available integrated circuit CFOAs AD844 in the frequency range up to about 10$$MHz is performed. The obtained results for the studied electronic circuits confirm the theoretical studies and hypotheses, and the comparative analysis shows that the maximum value for the relative error does not exceed 10%, which is acceptable considering the tolerances of the technological parameters of the used passive and active elements.

In the era of low-power very large-scale integration design, approximate computing is a soaring design paradigm that assures energy-efficient circuit design at the cost of some accuracy. Multiplication is a very important operation of an arithmetic unit and compressor is the inherent part of the multiplier. In this paper, an energy-efficient design of a 4:2 approximate compressor is proposed. The inclusion of the extra leakage control transistors in the logic has led to leakage power reduction, which ultimately reduces the power dissipation in the circuits. The proposed 4:2 compressor is simulated at 10$$nm fin-field effect transistor (FinFET) technology. The proposed compressor has been verified for its functionality and robustness. The proposed design shows a power dissipation of 154.48$$nW and a delay of 9.16$$ps. In comparison to other 4:2 approximate compressors, the proposed compressor shows the least power dissipation, the lowest power delay product (PDP) and the highest robustness. The power dissipation of the proposed compressor is 92.84% less than that of the base compressor. The PDP of the designed compressor is 80.58% less than the minimum PDP among other compressors. The aging analysis for the negative bias temperature instability (NBTI) effect is also checked for the proposed compressor and compared with the existing designs.

As Graphics Processing Units (GPUs) evolve for general-purpose computations besides inherently fault-tolerant graphics programs, soft error reliability becomes a first-class citizen in program design. Especially, safety-critical systems utilizing GPU devices need to employ fault-tolerance techniques to recover from errors in hardware components. While software-level redundancy approaches, based on the replication of the application code, offer high reliability for safe program execution, it is essential to perform redundancy by utilizing parallel execution units in the target architecture not to hurt performance with redundant computations. In this work, we propose redundancy approaches using the parallel GPU cores and implement a compiler-level redundancy framework that enables the programmer to configure the target GPGPU program for redundant execution. We run redundant executions for GPGPU programs from the PolyBench benchmark suite by applying our kernel-level redundancy approaches and evaluate their performance by considering the parallelism level of the programs. Our results reveal that redundancy approaches utilizing parallelism offered by GPU cores yield higher performance for redundant executions, while the programs that already make use of parallel GPU cores in their original form suffer from overhead caused by contention among redundant threads.

Low-resource utilization and high-energy consumption have become progressively protuberant issues in cloud data centers. Virtual Machine (VM) migration is the key objective to resolve this issue. Moreover, extreme VM migration might empower Service-Level Agreement (SLA) violations. Few works are considered for optimizing throughput and energy consumption. An efficient VM migration must consider different parameters like network communication overhead, migration overhead, resource utilization, energy consumption and quality of service which is a multi-objective issue. Hence, in this paper, a Modified Pelican Optimization-based Variable Load Mean Function (MPO-VLMF)-based host overload detection is presented and security enhancement is developed. The main motive of this study is to achieve host overload detection and security enhancement. To obtain host overload detection, the variable load mean function is developed. In this mean function, the weight parameter is selected by considering Modified Pelican Optimization (MPO). The Levy flight (LF) is considered for enhancing the updating process of Pelican Optimization (PO). To enhance the security of the system, the Digital Signature-based Encryption (DSE) is developed. Based on this proposed approach, security and host overload detection are obtained. The proposed technique is implemented and evaluated by performance measures. It is compared with the conventional approaches to justify the performance of the system.

This research paper presents a 12-bit 8–4-segmented current-steering DAC (digital-to-analog converter) that offers notable advantages, particularly in terms of its reduced power consumption compared to other similar designs. The exceptional performance of our DAC can be attributed to two key factors: the use of a thermometer encoder and an efficient digital input bit segmentation. These features contribute to enhanced precision and reduced power requirements, setting our DAC apart from the existing solutions in the field. These enhancements significantly reduce glitches and improve the accuracy of the DAC’s output. DAC dissipates a total power of about 44.95$$mW when running at a sample rate of 1.2$$GHz with the CMOS technology of 45$$nm. While the supply input voltage is held constant at 1.2$$V, the DAC’s digital input is pulsating in nature in which the ON voltage is 1$$V and OFF voltage is 0$$V. Also, the DAC has a spurious-free dynamic range (SFDR) of 41.77$$dB.

We implemented an ion-sensitive field effect transistor (ISFET) array chip comprising n-ISFET and p-ISFET for sensor application using 0.18$$$\mu$m CMOS technology. N-channel metal-oxide semiconductor (NMOS) and P-channel metal-oxide semiconductor (PMOS) ISFETs are fabricated in regular dimensions ($<$8$$$\mu$m) compatible with the standard CMOS process. We implemented n-ISFET cells and p-ISFET cells of different dimensions for characterization and to observe the possible effect of scalability. Each cell also has two identical NMOS and PMOS ISFETs of standard dimension, unlike very large dimensions ($>$200$$$\mu$m). We are using metals 1–6 and via together on the gate area to make it an extended or floating gate for the electrochemical sensing of ISFET. These metals are electrically floating with an intermediate dielectric. These different-size floating gate ISFETs provide different sensing areas, and the passivation Si₃N₄ layer is used for pH sensing without any extra post-processing measures. We observe the ISFET sensitivity and performance with the 0.18$$$\mu$m technology submicron effect. The measured results propose ISFET as a promising sensor device for portable applications. The ISFET chip dimension is 1179$$$\mu$m × 1185$$$\mu$m.

Within the frame of this work, a user-friendly MATLAB program for the simulation of signals and electronic noise at the nuclear radiation readout system was developed. Signal and noise in terms of equivalent noise charge (ENC) have been evaluated. Five noise sources were considered in order to have high simulation accuracy. The role and influence of different parameters of the readout circuits on the output signal and noise were predicted and illustrated. Moreover, the effect of all elementary parameters of each noise source on the ENC was taken into consideration. Since the energy resolution is affected by the electronic noise expressed by ENC, the obtained simulation results help to select the most feasible concept and parameters for a real system having a minimal noise effect. Using the program, several examples of the effect of those parameters on different ENC contributions related to the noise sources have been analyzed and discussed in detail. A comparison between the simulated results and experimental data was conducted.

In order to facilitate the high-quality advancement and digital innovation of the wine industry, a method based on principal component analysis (PCA) and improved quantum particle swarm optimization (IQPSO) to optimize support vector machine (PCA-IQPSO-SVM), was proposed to solve the wine classification problem. First, the feature extraction ability of PCA was used to reduce the input dimension of the model and improve the classification efficiency. At the same time, aiming at the problems that the quantum particle swarm optimization (QPSO) is easy to fall into local optimum and the convergence ability is decreased in the later stage of optimizing SVM, a variety of improvement strategies are used to improve QPSO to find the best parameters of SVM. The experimental results demonstrate that the model of PCA-IQPSO-SVM exhibits superior evaluation indices compared to other models. Moreover, the optimization efficiency of the PCA-IQPSO-SVM model is enhanced by 1.64% to reach an impressive 85.2%, showcasing its remarkable optimization effect. Simultaneously, this study provides a scientific approach for quality classification in the wine industry, thereby facilitating its high-quality development.