Analysis of Phase Noise in 28 nm CMOS LC Oscillator Differential Topologies: Armstrong, Colpitts, Hartley and Common-Source Cross-Coupled Pair

Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong di®erential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1GHz to 100GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of ̄ve distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of °icker noise contribution as the major e®ect leading to phase noise degradation in nanoscale CMOS LC oscillators.


Introduction
Advances in wireless communications have a great impact on our societal and economic challenges. [1][2][3][4][5] One of the most critical circuits of modern radiofrequency transceivers is the local oscillator, i.e., an autonomous circuit operating as the \pulsing heart" of such systems, in an analogy with the human body. As any other useful in extending the study to other oscillator topologies which may deserve our attention, such as the Armstrong topology. A recent implementation of this circuit topology shows potential for very low power operation, while achieving a high spectral purity. 15 This solution exploits integrated transformers 16,17 in order to implement magnetic coupling between gate and drain terminals, as well as source and drain terminals of the transistor pair in the oscillator.
Driven by the above motivations, in this paper we report a comparative investigation of PN in the common-source cross-coupled pair, Colpitts, Hartley and Armstrong di®erential oscillator topologies, with the main objective of bringing to the light the contributions of the inherent noise sources in the most widespread oscillator topologies reported in the literature. This comparative analysis extends and complements the previous analysis, 10 which was limited to Colpitts and Hartley singleended topologies and common-source cross-coupled di®erential pair. Here, the comparative analysis is extended to di®erential topologies for a fair comparison with the common-source cross-coupled di®erential pair and extended also to the Armstrong topology (in addition to Colpitts and Hartley). The oscillator circuit topologies are investigated under the common design conditions, such as (a) power consumption, (b) supply voltage, (c) transistor current density and (d) sizing (area, aspect ratio,¯nger width), (e) inductance and (f) quality factor of the integrated spiral inductors, (g) coupling factor of the integrated transformers and (h) considering the full models of the transistors available within the process design kit, including all their parasitic components related to their actual size, but excluding the layout interconnections, since the additional parasitic components introduced by the layout implementation could mask the results of the topological investigations which are the objectives of our study. The common conditions adopted in this comparative analysis are the same as those adopted for the comparative analysis between Colpitts and Hartley singleended topologies and common-source cross-coupled di®erential pair published in Ref. 10, thereby they represent the natural sequel from the previous results, which assures the continuity with them. As in the previous work, 10 the ISF is used to quantify the impact of each noise source on the overall PN in each oscillator circuit topology, allowing the identi¯cation of the major contributions to the PN degradation versus the oscillation frequency. The results could drive the designer through the choice of the oscillator circuit topology that could potentially o®er the best PN.
The paper is organized as follows. Section 2 describes the oscillator circuit topologies and their common design conditions. Section 3 reports the comparative analyses of PN. Section 4 reports the investigation on the contributions of each noise source to the overall PN. Finally, in Sec. 5 the conclusions are drawn. Figure 1 shows the oscillator circuit topologies designed in 28 nm bulk CMOS technology, operating from a 1 V supply voltage. All the circuit topologies operate in the voltage-limited regime. The same¯gure shows the current impulsive sources acting parallel to the inherent current noise sources and used for the evaluation of the ISF. Based on the¯ndings in Ref. 10, transient simulations were performed for an injected current amplitude of 1 A. The workload for the circuit simulations was signi¯cantly reduced by using OCEAN scripts. 18 The sizes of the active and passive devices are reported in Table 1. Capacitors are considered ideal, whereas a quality factor (Q) of 10 is assumed for the spiral inductors, i.e., a feasible value for the oscillation frequencies in the range of interest from 1 GHz to 100 GHz. 19,20 A coupling factor k of 0.85 is assumed for the transformers. 13 For all the investigated di®erential circuit topologies the total power consumption is 6.3 mW, as in Ref. 10. In particular, the comparative analysis takes into account the common-source cross-coupled di®erential pair, Colpitts, Hartley and Armstrong di®erential circuit topologies shown in Figs. 1(a)-1(d), which have shown the best PN performances with respect to other design variations. Thereby, these topologies allow an e®ective comparison based on the actual needs and opportunities, rather than a comparison between basic topologies and their variations which are known from the literature to provide worse PN performance with respect to those considered in this comparative analysis. In other words, the investigated topologies are the most promising in their category. The common-source cross-coupled pair in Fig. 1(a) provides the negative resistance needed for the oscillation start-up. A p-MOSFET is chosen as a current source since it exhibits lower°icker noise. The transformer coupling in the Colpitts topology of Fig. 1(b) contributes to the suppression of common-mode oscillations. 21 Moreover, for lower PN, two separate tail current transistors are used for biasing, as in Ref. 22. As for the Hartley topology in Fig. 1(c), the transformer coupling is used in order to reduce the area occupied by the inductors. 23 Finally, in the Armstrong topology of Fig. 1(d), the transformer coupling between gate and drain is considered for the same reasons. Also, in the latter topology, the inductance of the LC tank is given by the overall equivalent inductance o®ered by the self-inductance of the spiral inductors of the transformer and the mutual inductance between the two spirals on the gate and drain terminals of M 1 . The ISF allows us to determine the°icker and thermal noise contributions to the overall PN, as reported in Figs. 2-4. 11 Consequently, the 1/f 3 corner of the PN can be identi¯ed in each case. Table 2 provides the results for a 1 MHz frequency o®set from the carrier. The results show that the PN predicted by ISF matches well (within 1.7 dB) with the values obtained directly by means of SpectreRF simulations.

Comparison of Phase Noise Performance
From Table 2, it can be observed that under the adopted design conditions, common to all topologies, di®erential Armstrong topology reported here exhibits the lowest PN at an oscillation frequency of 1 GHz. The second best PN performance is Finally, at 100 GHz, the Hartley topology shows the best PN compared to the others. The Colpitts topology exhibits a PN higher than 10 dB with respect to Hartley. Then follows the common-source cross-coupled topology and last ranks Armstrong, which exhibit the worst PN. In order to gain a better understanding of the performances in between the initial discrete set of frequencies, the topologies have been designed also for the additional operating frequencies of 30, 50 and 70 GHz. The PN at a 1 MHz o®set from the carrier frequency obtained by direct plots from PSS and Pnoise simulations is shown in Fig. 5. By inspection, Fig. 5 reveals¯ve distinct regions in which the topologies rank unevenly in terms of best PN performance.
Region 1 (1-10 GHz): The Armstrong topology exhibits the lowest PN, whereas the Colpitts topology exhibits the worst one. In between, the common-source cross-coupled topology shows PN performance very close to that given by the Hartley topology.

Region 5 (70-100 GHz):
The di®erential Hartley is still characterized by the best PN, whereas Armstrong continues to exhibit the most degraded output signal spectrum. Here the Colpitts topology exhibits a better PN with respect to the common-source cross-coupled topology. In particular, their PN is on an average 3.5 and 2 dB, respectively, lower than di®erential Armstrong. Thereby, it can be concluded that for oscillation frequencies between 1 and 20 GHz, the Armstrong oscillator circuit topology considered here could be potentially the best choice. Outside this range, between 20 and 100 GHz, its performance dramatically deteriorates. For this oscillation frequency range, the di®erential Hartley topology considered in this study appears to be potentially the best choice. It is worth observing that the superior PN performance of the di®erential Hartley topology at high frequencies con¯rms with the results emerged from Ref. 10 for the single-ended Hartley topology.

Contributions of the Device Noise to Phase Noise
In order to get insight into the above results, in this section we report the evaluations of the contributions from each noise source in each oscillator circuit topology for a discrete set of oscillation frequencies from 1 GHz to 100 GHz, carried out by means of the ISF. The total thermal noise contribution to the PN, the latter traditionally indicated with L, from all m noise sources with a white power spectral density, can be expressed as 12 : where ð i 2 n Áf Þ i is the thermal noise generated from the ith noise source, q max is the charge injected into a circuit node by the noise source i n insisting in that node, À rms is the root mean square (rms) value of the ISF and Á! is the o®set from the oscillation angular frequency. The contribution of each noise source with white spectrum to the total thermal noise appearing at the output spectrum of the oscillator, the latter given by (1), is independent of the angular frequency o®set Á! as seen from (2).
Moreover, the total°icker contribution to the PN, from all n noise sources with a 1/f (°icker) spectrum can be expressed as follows 12 : Á! is the°icker noise generated from the ith noise source, À DC is the DC value of the ISF and ð! 1=f Þ i is the°icker noise corner of the ith active device. From (3) it can be concluded that larger oscillation amplitude leads to lower°icker noise contribution to PN, since q max ¼ C Â V max , where C is the total tank capacitance and V max is the maximum voltage swing across the tank. 12 The contribution of each°icker noise source to the total°icker noise appearing at the output spectrum of the oscillator, the latter given by (3), is independent from the angular frequency o®set Á! as noted from (4). total contributions of each device to PN at a frequency o®set of 1 MHz from the oscillation frequency. These results allow us to derive several important observations. For the 1 GHz oscillation frequency, in the common-source cross-coupled pair topology, the°icker noise sources of the cross-coupled pair contribute for about 65% to the°icker noise component of the PN, as shown in Fig. 6(a). From Fig. 7(a), it can be observed that only 13% of the thermal noise component of PN comes from the thermal noise of the cross-coupled pair. In spite of all, Fig. 8(a) shows that the total noise from the cross-coupled pair is the major contribution to the PN at a 1 MHz frequency o®set. This can be explained by noticing from Fig. 2(a) that the 1/f 3 corner of the PN is at the frequency o®set of 2 MHz. In the Colpitts topology, from Figs. 6(b) and 7(b) both the°icker noise and thermal noise components of the PN are mainly due to the tail current transistor pair M 3 . This explains why at a 1 MHz frequency o®set, the tail current transistor pair M 3 takes the largest portion of the total PN as reported in Fig. 8(b). With respect to the di®erential Hartley, the active device pair M 1 is the only source of°icker noise. In addition, the thermal noise generated by M 1 pair is mainly responsible for the white noise a®ecting the PN. This is why at a 1 MHz frequency o®set, the total noise contribution to PN is dominated by the M 1 common-source crossed-coupled pair.
Last, from Figs. 6(d) and 7(d) M 1 transistor pair in the Armstrong topology is responsible for about 65% and 60% of the PN components due to°icker noise and thermal noise, respectively. Thereby, it is also responsible for most of the total PN (62%) as shown in Fig. 8(d). For the oscillation frequency of 10 GHz, in the common-source cross-coupled pair topology, from Fig. 6(a) the cross-coupled pair M 1 is the major contributor to the°i cker noise component of PN. Also, at a 1 MHz o®set the PN spectrum is still at the 1/f 3 region according to Fig. 3(a). Thereby, the cross-coupled pair M 1 is expected to be the dominant source of the overall PN as con¯rmed from Fig. 8(a).
As for the Colpitts topology, the°icker contribution of the tail current transistor pair M 3 is predominant. Thereby, for the same reason as above, the tail current noise is the major contributor to PN at a 1 MHz frequency o®set.
The pair of transistors M 1 in di®erential Hartley is almost the sole source of noise. This is because the noise generated by the parasitic resistance of the inductors is at least one order of magnitude lower than the°icker and thermal noise of the active device pair M 1 .
Finally, the tail current transistor M 4 in the Armstrong topology is mostly responsible for the°icker component of PN. Moreover, the 1/f 3 PN corner is at 2.1 MHz, as depicted in Fig. 3(d). Therefore, at a 1 MHz o®set the tail current transistor M 4 presents the main contribution to the overall PN.
For the oscillation frequency of 100 GHz, the 1/f 3  In the Colpitts topology,°icker and thermal noise contributions to PN are mainly due to M 1 transistor pair. Thereby, the pair of transistors M 1 represents the noise source which is mainly responsible for the PN at a 1 MHz frequency o®set.
In the Hartley topology, the active device pair M 1 is the only°icker noise source, which dominates the PN at a 1 MHz frequency o®set.
In the Armstrong topology, almost equal contribution to the°icker and thermal noise components of PN from the M 1 transistor pair and the tail current transistor M 4 , also means equal contribution to the overall PN at a 1 MHz frequency o®set.
From all the above, we can conclude that, for all four topologies and for the oscillation frequencies of 10 and 100 GHz, the 1/f 3 region of the PN extends above 1 MHz. At an oscillation frequency of 1 GHz, this is true for the common-source crosscoupled pair and for the Hartley topologies. This is a consequence of the adoption of nanoscale CMOS technologies characterized by°icker noise corners of several tens or hundreds of MHz, which lead to°icker noise up-conversion being responsible for most of PN 24,25 even at large o®sets from the carrier frequency. This means that the devices with the highest contribution to the°icker noise presented at the output spectrum will also dominate PN. Hence, design e®orts should be made in minimizing the°icker noise sources as much as possible, as well as°icker noise up-conversion characteristic mechanisms in each topology. For example, increasing the width of the cross-coupled devices of Fig. 1(a) would reduce the°icker noise produced by the transistor pair M 1 . On the other hand,°icker noise up-conversion gain would be increased. This is due to the increased small-signal loop gain which would in turn cause a higher distortion of the voltage output. 25,26 As another example, a¯ltering technique adopting a resonant¯lter could also be adopted for reducing°icker noise up-conversion. 27 For the oscillation frequency of 1 GHz, in the Colpitts and Armstrong topologies the 1/f 3 PN corners are below the 1 MHz frequency o®set. In this case, the active or passive devices with the highest contribution to the thermal noise component of the PN will be dominant. Short channel e®ects such as velocity saturation and channel length modulation are responsible for the signi¯cant increase in the thermal noise excess factor in deep submicron CMOS technologies. 28,29 Thus, thermal noise from the active devices is usually the principal source of white noise in the output spectrum as already observed from Figs. 6-8.
The theoretical expressions of the overall PN including all its contributions that could allow us to distinguish between the nature of the°icker noise contributions due to the up-conversation mechanisms identi¯ed in the literature 25 could be addressed in future works. Theoretical analysis of°icker noise up-conversion is outside the scope of this manuscript, for which we refer to the existing literature. 25,30,31 However, it is worth observing that due to the absence of varactor,°icker noise up-conversion is caused mainly by (a) amplitude to PN conversion due to nonlinear transconductor parasitic capacitance, as well as by (b) modulation of the harmonic content of the output voltage waveform, i.e., Groszkowski e®ect. 25 Reference 30 reports an analysis which is based on the ideal quadratic I-V MOS characteristic, and, as such, quantitatively valid only for long-channel transistors. Thereby, the conclusion reported therein 30 that there is no up-conversion of 1/f noise into PN from the core MOS transistors (M 1 ) does not apply to the oscillator circuit topologies investigated in this manuscript since they adopt short channel MOSFETs of the 28 nm bulk CMOS technology.

Conclusions
Comparative analyses of phase noise were carried out for four di®erential oscillator circuit topologies: common-source cross-coupled pair, Colpitts, Hartley and Armstrong. The oscillator circuit topologies were designed in a 28 nm bulk CMOS technology, for a set of operating frequencies in the range from 1 GHz to 100 GHz. All the topologies were investigated under the same common design conditions, such as power consumption, supply voltage, transistor current density and sizing, inductance and quality factor of the integrated spiral inductors, coupling factor of the integrated transformers, and considering the full models of the transistors available within the process design kit, including all their parasitic components related to their actual size. Furthermore, the phase noise results from PSS and Pnoise simulations were compared with phase noise predictions obtained by the ISF. Finally, the noise contributions from each active or passive device in the circuit topologies to the°icker and thermal phase noise components and to the overall phase noise at a 1 MHz frequency o®set from carrier frequency were evaluated and discussed.
The results show that, under the adopted design conditions, the phase noise of the four topologies degrades unevenly over the considered oscillation frequency range. In particular, the comparative analyses show the existence of¯ve distinct frequency regions. Thereby, the results presented here suggest that the identi¯cation of the best oscillator circuit topology in terms of phase noise is related to the operating frequency range. Consequently, these results suggest the opportunity to address further investigations on the Armstrong and Hartley topologies considered in this study. The investigations could allow us to extend the range of possibilities beyond the common practice of choosing the common-source cross-coupled di®erential pair topology, traditionally selected for its reliable start-up, but without further topological considerations.
Finally, the investigations through the ISF allowed the identi¯cation of the dominant noise contributions for each oscillator circuit topology. Despite a few exceptions, the results showed that the°icker noise from the active devices is the component with the most signi¯cant e®ect on the oscillator phase noise at a 1 MHz frequency o®set from the carrier frequency, con¯rming the rising role of°icker noise in nanoscale CMOS technology.