World Scientific
  • Search
Skip main navigation

Cookies Notification

We use cookies on this site to enhance your user experience. By continuing to browse the site, you consent to the use of our cookies. Learn More
×
Our website is made possible by displaying certain online content using javascript.
In order to view the full content, please disable your ad blocker or whitelist our website www.worldscientific.com.

System Upgrade on Tue, Oct 25th, 2022 at 2am (EDT)

Existing users will be able to log into the site and access content. However, E-commerce and registration of new users may not be available for up to 12 hours.
For online purchase, please visit us again. Contact us at [email protected] for any enquiries.

A 2.5 GHZ CMOS MIXER WITH IMPROVED LINEARITY

    A new linearization technique for a CMOS high frequency mixer will be presented. The reduction of the total harmonic distortion coefficient is achieved by replacing the simple differential amplifier from the basic multiplier circuit with a cross-connection differential amplifier, with the advantage of canceling the third-order harmonic from the output signal expression. The circuit was implemented in 0.35 μm CMOS technology and it was supplied at a total voltage of 6 V. The transient and Fourier analysis for high frequency input signals (ω1 = ω2 = 2.5 GHz and ω1 = 2.5 GHz; ω2 = 2.25 GHz) confirm the theoretical estimated results (an improvement in linearity of about 8 dB).

    This paper was recommended by Regional Editor Piero Malcovati.

    References

    • C. Kuan-Hung and C. Yuan-Sun, IEEE Trans. Very Large Scale Integration Systems 846 (2007). Google Scholar
    • S. Desai, P. Trivedi and V. Von Kanael, A dual-supply 0.2-to-4 GHz PLL clock multiplier in a 65 nm dual-oxide CMOS process, Solid-State Circuits Conf., ISSCC 2007, Digest of Technical Papers. IEEE Int., 11–15 February 2007, pp. 308–311 . Google Scholar
    • E. Bergeret, J. Gaubert and P. Pannier, Standard CMOS voltage multipliers architectures for UHF RFID applications: Study and implementation, RFID, 2007, IEEE Int. Conf. (2007) pp. 115–120. Google Scholar
    • C. Popa, Scientific Bulletin, University "Politehnica" of Bucharest 62, 51 (2000). Google Scholar
    • C. Popa, Linear rail-to-rail CMOS input stage, 13th Int. Conf. Control System and Computer Science (University "Politehnica" of Bucharest, 2001) p. 536. Google Scholar
    • C. Hunget al., Low-voltage rail-to-rail CMOS differential difference amplifier, IEEE Proc. Int. Symp. Circuits and Systems (1997) p. 145. Google Scholar
    • A. Hyogo, Y. Fukutomi and K. Sekine, Low voltage four-quadrant analog multiplier using square-root circuit based on CMOS pair, IEEE Proc. Int. Symp. Circuits and Systems (1999) p. 274. Google Scholar
    • D. Manstretta, M. Brandolini and F. Svelto, Solid-State Circuits, IEEE J. 38, 394 (2003), DOI: 10.1109/JSSC.2002.808310. CrossrefGoogle Scholar
    • M. T. Terrovitis and R. G. Meyer, Solid-State Circuits, IEEE J. 35, 1461 (2000), DOI: 10.1109/4.871323. CrossrefGoogle Scholar