A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.