HIGH LEVEL SIMULATION OF SVP MANY-CORE SYSTEMS
Abstract
The Microgrid is a many-core architecture comprising multiple clusters of fine-grained multi-threaded cores. The SVP API supported by the cores allows for the asynchronous delegation of work to different clusters of cores which can be acquired dynamically. We want to explore the execution of complex applications and their interaction with dynamically allocated resources. To date, any evaluation of the Microgrid has used a detailed emulation with a cycle accurate simulation of the execution time. Although the emulator can be used to evaluate small program kernels, it only executes at a rate of 100K instructions per second, divided over the number of emulated cores. This makes it inefficient to evaluate a complex application executing on many cores using dynamic allocation of clusters. In order to obtain a more efficient evaluation we have developed a co-simulation environment that executes high level SVP control code but which abstracts the scheduling of the low-level threads using two different techniques. The co-simulation is evaluated for both performance and simulation accuracy.
References
- IEEE Trans. Comput. 54(6), 684 (2005), DOI: 10.1109/TC.2005.103. Crossref, ISI, Google Scholar
- ACM Trans. Des. Autom. Electron. Syst. 10(3), 431 (2005), DOI: 10.1145/1080334.1080335. Crossref, ISI, Google Scholar
- IEEE Trans. Comput. 55(2), 99 (2006), DOI: 10.1109/TC.2006.16. Crossref, ISI, Google Scholar
- IEEE Micro 23, 26 (2003), DOI: 10.1109/MM.2003.1240210. Crossref, Google Scholar
- SIGARCH Comput. Archit. News 32(2), 350 (2004), DOI: 10.1145/1028176.1006730. Crossref, Google Scholar
- IEEE Trans. Comput. 57(1), 41 (2008), DOI: 10.1109/TC.2007.70783. Crossref, ISI, Google Scholar
- IEEE Transactions on Computers 58, 1668 (2009), DOI: 10.1109/TC.2009.77. Crossref, ISI, Google Scholar
S. Nussbaum and J. E. Smith , Statistical simulation of symmetric multiprocessor systems, SS '02: Proceedings of the 35th Annual Simulation Symposium (IEEE Computer Society, 2002) p. 89. Google Scholar- Advances in Parallel Computing 16, 37 (2008). ISI, Google Scholar
- SIGARCH Comput. Archit. News 37(2), 38 (2009), DOI: 10.1145/1577129.1577136. Crossref, Google Scholar
- Journal of Systems Architecture 55(3), 149 (2009), DOI: 10.1016/j.sysarc.2008.07.001. Crossref, ISI, Google Scholar
T. D. Vu and C. R. Jesshope , Formalizing SANE virtual processor in thread algebra, ICFEM (2007) pp. 345–365. Google ScholarK. Gharachorloo , Memory consistency and event ordering in scalable shared-memory multiprocessors, ISCA '90: Proceedings of the 17th annual international symposium on Computer Architecture (ACM, 1990) pp. 15–26. Google Scholar- Journal of Systems Architecture 55(3), 162 (2009), DOI: 10.1016/j.sysarc.2008.09.006. Crossref, ISI, Google Scholar
- International Journal of Parallel Programming 34(4), 383 (2006), DOI: 10.1007/s10766-006-0018-x. Crossref, ISI, Google Scholar
- Journal of Functional Programming 15(3), 353 (2005). Crossref, ISI, Google Scholar
- IBM J. Res. Dev. 34(1), 12 (1990), DOI: 10.1147/rd.341.0012. Crossref, ISI, Google Scholar
- ACM Trans. Model. Comput. Simul. 7(1), 78 (1997), DOI: 10.1145/244804.244807. Crossref, Google Scholar
- Computer 35(2), 50 (2002), DOI: 10.1109/2.982916. Crossref, ISI, Google Scholar
- Computer 35(2), 59 (2002), DOI: 10.1109/2.982917. Crossref, ISI, Google Scholar
- SIGOPS Oper. Syst. Rev. 43(1), 52 (2009), DOI: 10.1145/1496909.1496921. Crossref, Google Scholar
A. S. Cassidy , J. M. Paul and D. E. Thomas , Layered, multi-threaded, high-level performance design, DATE '03: Proceedings of the conference on Design, Automation and Test in Europe (IEEE Computer Society, 2003) p. 10954. Google ScholarD. Brooks , V. Tiwari and M. Martonosi , Wattch: A framework for architectural-level power analysis and optimizations, ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture (ACM, 2000) pp. 83–94. Google ScholarS. Nussbaum and J. E. Smith , Modeling superscalar processors via statistical simulation, PACT '01: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (IEEE Computer Society, 2001) pp. 15–24. Google Scholar- SIGARCH Comput. Archit. News 25(3), 13 (1997), DOI: 10.1145/268806.268810. Crossref, Google Scholar
- SIGARCH Comput. Archit. News 37(2), 10 (2009), DOI: 10.1145/1577129.1577133. Crossref, Google Scholar
D. Genbrugge , S. Eyerman and L. Eeckhout , Interval simulation: Raising the level of abstraction in architectural simulation, HPCA (2010) pp. 1–12. Google ScholarJ. Shin , A 40nm 16-core 128-thread CMT SPARC SoC processor, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International (2010) pp. 98–99. Google Scholar


