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Special Section on Radiation Effects and Fault Tolerance in Electronic Devices, Circuits, and Systems
Guest Editors: M. Krstic (University of Potsdam, Germany) and M. Carvajal (University of Granada, Spain)
Open Access

Response of Commercial P-Channel Power VDMOS Transistors to Ionizing Irradiation and Bias Temperature Stress

    https://doi.org/10.1142/S0218126622400035Cited by:1 (Source: Crossref)

    In this paper, the effects of successively applied static/pulsed negative bias temperature (NBT) stress and irradiation on commercial p-channel power vertical double-diffused metal-oxide semiconductor (VDMOS) transistors are investigated. To further illustrate the impacts of these stresses on the power devices, the relative contributions of gate oxide charge (Not) and interface traps (Nit) to threshold voltage shifts are shown and studied. It was shown that when irradiation without gate voltage is used, the duration of the pre-irradiation static NBT stress has a slightly larger effect on the radiation response of power VDMOS transistors. Regarding the fact that the investigated components are more likely to function in the dynamic mode than the static mode in practice, additional analysis was focused on the results obtained during the pulsed NBT stress after irradiation. For the components subjected to the pulsed NBT stress after the irradiation, the effects of Not neutralization and Nit passivation (usually related to annealing) are more enhanced than the components subjected to the static NBT stress, because only a high temperature is applied during the pulse-off state. It was observed that in devices previously irradiated with gate voltage applied, the decrease of threshold voltage shift is significantly greater during the pulsed NBT stress than during the static NBT stress.

    This paper was recommended by Regional Editor Zoran Stamenkovic.

    Extended paper from MIEL 2021 Conference to Journal of Circuits, Systems, and Computers.1

    References